A Comprehensive Analysis of Different SRAM Cell Topologies in 7-nm FinFET Technology

Complementary metal-oxide-semiconductor (CMOS) device faces various unknown short channel effects (SCEs) such as subthreshold leakage and drain-induced barrier lowering (DIBL) in advanced technologies. This degrades the circuit’s performance, especially SRAM cell, owing to high demand for large density. Fin-shaped field-effect transistor (FinFET) is one of trending choices memory designers, which can improve stability minimize SCEs CMOS devices. In this study, different cell topologies are redesigned re-simulated by using 7-nm FinFET devices, then, their performance metrics including stability, access time, power measured at a certain range supply voltage (VDD) below nominal value 0.7 V. Moreover, layout these cells designed compared ST12T consumes maximum area due having higher count transistors. Simulated results inferred that ST11T offers highest RSNM among all cells, be explained with use read decoupling technique cross-coupled Schmitt-trigger inverters. has WSNM comparison other because performs its write operation fully differential form along power-gating write-assist technique. view consumption, least dynamic dissipation, respectively, former single-ended bitcell low frequency latter stacked transistors core path from VDD GND long. An electrical quality metric (EQM) utilized assess overall displays superiority cell.